Mohammad Mortazavi

Sharif University of Technology

 

 

Home

SPECIAL INTERESTS:

Developments of VLSI CAD Tools

ASIC/FPGA Based Design Methodologies

Transistor and Gate-level Static Timing Verification

Signal Integrity & Crosstalk Verifications

Physical Design Layout Synthesis

EXPERIENCE:

1. August 2006 to Present- Adjunct Professor, Electrical Engineering Department, Sharif University of Technology,ASIC/FPGA Based Chip Designs ,Hardware Design Interfaces (Madar Vaset) ,Introduction to VLSI Design Systems

2. January 2006 to April 2007- Director of Engineering, Microelectronic Research & Development Center of Iran (MERDCI), Tehran, Iran

3. January 2005 to December 2005- Senior Timing Manager, Tera Systems, San Jose, CA

4. July 2000-April 2005- Senior Member of Consulting Staff, Digital IC Business Unit of Cadence Design Systems, San Jose, CA

5. July 1995-April 2000- Senior Member of Technical Staff, Custom IC Business Unit of Cadence Design Systems, San Jose, CA

6. August 1991-May 1995- Research Assistant: State University New York (SUNY)

7. May 1992-December 1992-Intern Engineer: Laser Tech Associates, Johnson City, NY

PATENTS

1. Transistor-Level Timing Analysis Using Embedded Simulation, Pending 2007

2. System and method for timing abstraction of digital logic circuits, April 15, 2005, Patent #6,877,143

3. Functional timing analysis for characterization of virtual component blocks, September 24, 2002, Patent #6,457,159

4. System and method for timing abstraction of digital logic circuits, August 27, 2002, patent #6,442,739

AWARDS

1.1994 Recipient of best paper award in IEEE Autotestcon Conference

2.1985-1989 Recipient of Marine Midland Scholarship in achievement of Mathematics and Science.

EDUCATION

Ph.D., MS, BS in Electrical Engineering, 1995, 1992, 1989   

State University of New York (SUNY)

Ph.D. Dissertation:  A VLSI Layout Methodology For Floor-planning, Placement Synthesis, and Compaction.

Master Thesis: Development of a Mathematical Description, Analysis & Development of Decoupling Control Systems for a dc Generator.

Address: Azadi Ave, Tehran, Iran

Electrical Engineering Department

Sharif University of Technology

To contact us:

E-mail: mortazavi@sharif.edu